A universal asynchronous receiver/transmitter (UART) controller is a key device or component that is utilized for serial communication. The UART may be adapted to take bytes of data and transmit individual bits in a sequential fashion. At a destination, a second UART may be adapted to re-assemble these individual bits into complete bytes.
Serial transmission may be used for communication between computers, terminals, modems and other non-networked devices. There are two primary forms of serial transmission: synchronous serial transmission and asynchronous serial transmission. Synchronous serial transmission may require that a sender and receiver share a common clock, or that the sender may provide timing in the form of a strobe or other timing signal so that the receiver knows when to read the next bit of data. Synchronous communication is usually more efficient because only data bits are transmitted between a sender and a receiver, but may be more expensive as extra wiring and circuits may be required to share a clock signal between the sender and receiver. A form of synchronous serial transmission is used with printers and fixed disk devices, which allow data to be sent out on one set of wires while a clock or strobe may be sent on a different wire.
Asynchronous serial transmission may allow data to be transmitted without the sender having to send a clock signal to the receiver. The sender and receiver may agree on timing parameters in advance and special bits may be added to each word that is used to synchronize sending and receiving units. When a word of data is sent to a UART for asynchronous serial transmission, a bit, for example, a start bit may be added before each word to be transmitted. The start bit may be used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. These two clocks may be accurate enough to prevent a frequency drift during transmission of remaining bits in the word of data. After the start bit is sent out, individual bits of the word of data may be sent with the least significant bit (LSB) being sent first. When an entire word of data has been sent, a parity bit may be added that is generated by a transmitter. The parity bit may be used by the receiver to perform simple error checking. The transmitter at the end of transmission may send at least one stop bit. When the receiver has received all bits in the word of data, it may check for the parity bits and the stop bit. If the stop bit fails to appear, the UART may consider the entire word of data to be garbled and may report a framing error to a host processor when the word of data is read.
FIG. 1 is a block diagram of an exemplary system illustrating serial communication utilizing UART auto flow control. Referring to FIG. 1, there is shown digital terminal equipment (DTE) 102, digital communication equipment (DCE) 104, two UART's 106 and 108 and a serial communication interface 110. The digital terminal equipment (DTE) 102 may be, for example, a computer that may be adapted to transmit and receive data. The digital communication equipment (DCE) 104 may be, for example, a modem that may be utilized to provide a modulation/demodulation interface between the digital terminal equipment (DTE) 102 and a transmission circuit. The universal asynchronous receiver/transmitter UART 106 and 108 may be adapted to perform parallel-to-serial conversion of digital data to be transmitted and serial-to-parallel conversion of digital data that has been transmitted. The serial communication interface 110 may comprise a plurality of wires that may be coupled so as to implement serial communication.
In operation, serial communication may comprise transmission of one bit of information at a time. The UART 106 and 108 may be utilized as interface chips to implement serial data transmission across the serial communication interface 110. A full-duplex communication system may allow information to be transferred simultaneously in both directions between the DTE 102 and the DCE 104. A half-duplex communication system may allow information to be transferred in both directions between the DTE 102 and the DCE 104, but in only one direction at a time. A simplex communication system may allow information to be transferred in only one direction.
FIG. 2 is a timing diagram illustrating a frame of data that may be transmitted during serial communication utilizing UART auto flow control. Referring to FIG. 2, there is shown a frame of data 200 that comprises one or more idle bits 202, a start bit 204, a 7 bit data frame 206, a parity bit 208 and one or more stop bits 210. The frame of data 200 may be a complete and nondivisible packet of bits and may be a smallest packet of data that may be transmitted. In the RS232 protocol, the idle bit 202 may be true indicating a low voltage level, for example, −12 V, while the start bit 204 may be false indicating a high voltage level, for example, +12 V. The start bit 204 may indicate a start of transmission of data. The parity bit 208 may be utilized to detect errors during transmission of data. To detect even parity, a sum of number of 1's in the frame of data 200 and the parity bit 208 is an even number. Similarly, to detect odd parity, a sum of number of 1's in the frame of data 200 and the parity bit 208 is an odd number. The stop bit 210 may be utilized to signal the end of transmission of data. The RS232 and RS422 protocols may require a frame of data to have a start bit 204, a plurality of data bits 206, a parity bit 208 and one or more stop bits 210.
Most mobile devices such as laptops, PDA's and cell phones, for example are designed to conserve battery life by switching to a sleep mode when the device is not active. In this regard, one or more processors within a particular device may be configured to enter sleep mode, or some power saving mode when the device detects a period of inactivity. For example, the sleep mode automatically turns off a device after it has been unused for a predetermined period of time so as to conserve battery life. When a device is in sleep mode and data is sent to the device, the device takes a while before it wakes up and enters an operational state where it processes the received data. As a result, the device may miss some of the initial characters because of the inherent delay in waking up. Even though some systems may minimize the wakeup time, characters may still be lost.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.